Time cycles

To set the strobe, and then sets its. Like the PWM generator, It can't be set at any other time, not dictated by the edges of the instruction clock. Last edited: Sep 17, 2020 #18 If that is true, then the diagrams are not correct and my question is answered. A PWM and instruction set (program counter) clocked by the same source must be in sync. I can't set the strobe at a random time. It is is set when the instruction clock steps to the line in code to set the strobe, and then sets its. Like the PWM generator, It can't be set at any other time, not dictated by the edges of the instruction clock. No.Your PWM cycle repeats every 81 instruction cycles. If you set the strobe on the 15th instruction cycle, then it's going to occur ~15 instruction cycles after the PWM. If next time you set the strobe on the 140th instruction cycle, it's going to be ~60 instruction cycles past the PWM.Post some code describing setting the strobe pin, and/or ADC sampling. #19 No.Your PWM cycle repeats every 81 instruction cycles. If you set the strobe on the 15th instruction cycle, then it's going to occur ~15 instruction cycles after the PWM. If next time you set the strobe on the 140th instruction cycle, it's going to be ~60 instruction cycles past the PWM.Post some code describing setting the strobe pin, and/or ADC sampling. I totally agree with that, and that's not a problem. Regardless of how many instruction cycles it takes to produce a PWM cycle or to produce a strobe, the edges of both the PWM output and the Strobe occur on transitions of the instruction clock, and only on transitions of the instruction clock, if the documentation is correct. Showing specific code is not relevant to the bigger picture about synchronization. So, if I sync the scope on the strobe, an edge of the PWM output might be one or more instruction clock cycles away from the strobe, or even a variable number of instruction clock cycles, but never a period time that is not a multiple of the instruction clock, right? #20 Durr, hold everything. They ARE synchronized. It's just my scope setup. The instruction clock is so much faster than the PWM signal that with the time scale I was using, it just appeared that that they are not synchronized because of the edges being so close together!Thanks guys for being ears and voices to help me think and talk through this. That helps a lot.Looking back I also misstated the problem and what I was expecting, and threw some folk off. Sorry about that. Sometimes my fingers don't type what the mind is really thinking. I should have said the MINIMUM amount of time between the strobe and PWM edges should be constant. Last edited: Sep 18, 2020 Status Not open for further replies. Similar threads Electronics Forums Microcontrollers This site uses cookies to help personalise content,

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Erased each time before programming with new data. Each pair of erase and program operations is called a P/E cycle [20]. However, after repeated program/erase operations are performed on the block, the amount of charge trapped in the tunnel oxide layer increases. The trapped charges make it difficult for the NAND cells’ threshold voltage levels to remain within their expected voltage range, which significantly affects the reliability of the NAND cells [10,21]. In other words, flash blocks can only go through a limited number of P/E cycles before they wear out. As the P/E cycle increases, the BER of the data in the block increases gradually [22], resulting in errors in the data stored in the cells.For reliability reasons, when the BER of a page exceeds the error correction capability of the ECC engine, manufacturers believe that the P/E cycles that the page has experienced at this time are the maximum P/E cycles that the page can experience, that is, the NAND’s endurance [23]. Due to the process variation of 3D NAND, the endurance of each layer of pages is different, and the maximum P/E cycles it can experience are also different. However, when the BER of any page in the block exceeds the ECC error correction capability, the entire block will be considered a bad block [24]. In other words, the number of maximum allowed P/E cycles of a block depends on the P/E cycles that the least endurable page in the block can experience; there are inclined to